Typically, a computer system contains a processor, a bus, and other peripheral devices. The processor is responsible for executing instructions using the data in the computer system. The bus is used by the microprocessor and the peripheral devices for transferring information between one another. The information on the bus usually includes data, address and control signals. The peripheral devices comprise storage devices, input/output I/O devices, etc. Generally, all operations being performed in the computer system occur at the same frequency.
The microprocessor has a core for processing the data. Since generally all operations performed by the computer system occur at the same frequency, the logic operations performed by the core are at the same frequency as the transfer of data, address and control signals on the computer system bus.
Some logic operations performed by the core, such as arithmetic operations, require multiple cycles to complete. During completion of these multiple cycle operations, the bus remains idle. It is desirable to have the core operate at a faster speed than the bus, so that operations are performed more quickly. In this manner, the bus will be used more frequently, such that bus idle states will be reduced and operations performed more quickly.
Many techniques exist to reduce the power consumed by the processor. One technique for this has been to stop the processor regardless of the current instruction being executed. Methods have been employed whereby the processor is stopped on predetermined conditions. Another mechanism used in the prior art causes the processor to stop asynchronously by disabling the externally generated clock signal utilized to generate the internal clock of the device.
A problem with asynchronously disabling the external reference frequency generator involves the fact that most microprocessors and computer systems utilize a phase-locked loop (PLL) circuit to multiply the reference frequency by some factor to generate the system's internal clock rate. The internal clock signal is utilized by the central processing unit (CPU) of the computer during the execution of its various functions and instructions. A problem arises is that if the clock is stopped externally, then the internal phase-locked loop circuitry is likewise disabled. Under such circumstances, reenabling the external reference frequency does not produce an instantaneous response from the PLL. In other words, the PLL requires some fixed time period (e.g., hundreds of microseconds) to stabilize and achieve lock. During this start-up time period, spurious signals and glitches are commonly generated, leading to unpredictable results. Thus, starting and stopping of the processor's clock by disabling the external reference input frequency results in a loss of pseudoinstantaneous response. What is needed is a means for reducing power consumption in a processor which does not cause a PLL in a computer system to become unstabilized, such that spurious signals and glitches result. That is, it is desirable to have a mechanism for reducing power in a processor which can be utilized such that the remainder of the computer system is unaware of its use (i.e., it is transparent).
When additional features are integrated in a microprocessor, its use most often requires changes to the computer system to accommodate the new features. These changes could take the form of modifications to the circuit board, including adding extra circuitry. Ideally, new features and faster processing should be added without changing, for example, the mother board of a computer system. It is thus advantageous to modify microprocessors by incorporating new features in such a way as to reduce or dispense with changes to the remainder of the computer system. It is also advantageous to keep the number of hardware changes small so that preexisting computer applications can benefit by upgrading their computer systems without having to acquire new system components, thereby avoiding huge expenditures.
The present invention provides a means for powering down the processor when the processor is in an idle state. The present invention provides a means for powering down a processor that is transparent to the computer system, such that the processor is able to enter and exit the reduced power consumption state without the remainder of the computer system knowing.